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AUIRS2336S
LINx
HINx
50%
50%
LOx
HOx
50%
DT
DT
50%
Figure 7: Illustration of deadtime
Matched Propagation Delays
The AUIRS2336S is designed with propagation delay matching circuitry. With this feature, the IC’s response at the
output to a signal at the input requires approximately the same time duration (i.e., t ON , t OFF ) for both the low-side
channels and the high-side channels; the maximum difference is specified by the delay matching parameter (MT).
Additionally, the propagation delay for each low-side channel is matched when compared to the other low-side
channels and the propagation delays of the high-side channels are matched with each other; the MT specification
applies as well. The propagation turn-on delay (t ON ) of the AUIRS2336S is matched to the propagation turn-on delay
(t OFF ).
Input Logic Compatibility
The inputs of this IC are compatible with standard CMOS and TTL outputs. The AUIRS2336S has been designed to
be compatible with 3.3 V and 5 V logic-level signals. It features an integrated 5.2 V Zener clamp on the HIN, LIN,
ITRIP, and EN pins; Figure 8 illustrates an input signal, its input threshold values, and the logic state of the IC as a
result of the input signal.
V IH
V IL
High
Low
www.irf.com
Low
Figure 8: HIN & LIN input thresholds
17
? 2009 International Rectifier
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